问题描述
在英特尔处理器，每个核心拥有自己的L1的L2缓存。这是ARM的双核处理器是真的吗？如果是这样，我可以依靠两个内核之间的缓存一致性，使得在核心0运行的线程总会看到在其缓存中的数据相同的核心1在其看到了什么？
On Intel processors, each core has its own L1 an L2 caches. Is this true on the ARM dual-core processors? If so, can I rely on cache coherency between the two cores, such that a thread running on core 0 will always see the same data in its cache that core 1 see in its?
推荐答案
你的意思是ARMv7的？我不认为有一个ARM7双核心，你可以把两个芯片肯定，但他们是独立的（和他们没有配备缓存，所以你就必须实现自己的）。
Do you mean ARMv7? I dont think there is an ARM7 dual core, you could put two in a chip sure but they would be independent (and they didnt come with caches so you would have to implement your own).
下面是与ARM的故事，而不是真的有什么不同，除了比英特尔英特尔是芯片业务，手臂是他们不制造芯片的IP业务。
Here is the story with ARM, not really any different than intel except intel is in the chip business, arm is in the IP business they dont make chips.
在开始创建一个免费帐户的一些文档中，在的ARMv7尤其是你将需要登录。
start at http://infocenter.arm.com create a free account some of the docs, ARMv7 in particular you are going to need to log in.
有两种类型的ARM文档中。有ARM的ARM是ARM的架构参考手册的。曾经是一个大的人工覆盖所有的核心，现在它被分成核心家庭覆盖整体的相似之处，指令集等为家庭核心。既然你是问有关双/多核你很可能在谈论的Cortex-A的ARMv7-A（不是ARMv7-M架构这些都是单核心微控制器）。或者，也许你的意思是ARMv6内核像其中有一到四个核心变种MPCore的。在根据内容沿左信息中心的网站，你选择ARM架构的话，第一件事就是参考手册。这就像胳膊文档，家庭医生的全科医生，而不是在任何领域的专家才知道一些有关的一切。
There are two types of ARM docs. There are the ARM ARM's the ARM Architectural Reference Manual's. Used to be one big manual covering all the cores, now it is broken into core families covering the overall similarities, instruction set, etc for a family of cores. Since you are asking about dual/multi core you are likely talking about the Cortex-A ARMv7-A (not the ARMv7-M those are single core microcontrollers). Or maybe you meant the ARMv6 cores like the mpcore which has a one to four core variant. On the infocenter site along the left under contents you select arm architecture then the first thing is reference manuals. This is like the general practitioner of arm docs, the family doctor, not a specialist in any field just knows something about everything.
第二型臂DOC的是TRM，技术参考手册，这是专家，脑外科医生或足病诊疗师，等你发现，芯片供应商正在使用（可以很容易或硬取决于特定的核心芯片和供应商），并且将描述什么芯的边缘看起来像是将描述其中缓存是，谁共享与否以及如何。需要注意的是L1缓存和MMU经常在TRM为核心，二级缓存是一个额外的成本项目，不一定由芯片供应商处购买。 L1缓存，也没有MMU，不一定坐在AMBA，AXI总线，二级是，AMBA / AXI出垫片的AMBA / AXI，修改或消费的交易，因为他们去了，你还是把你的记忆系统在外层AMBA / AXI。
The second type of arm doc is the TRM, the technical reference manual, this is the specialist, the brain surgeon or podiatrist, etc. You find the specific core that the chip vendor is using (can be easy or hard depending on the chip and vendor) and that will describe what the edges of the core look like it will describe where the caches are, who shares them or not and how. Note that the L1 cache and mmu are often in the TRM for the core, the L2 cache is an extra cost item, not necessarily purchased by the chip vendor. the L1 cache, nor mmu, does not necessarily sit on the amba, axi bus, the l2 is an amba/axi in, amba/axi out shim, modifying or consuming transactions as they go by, you still have to put your memory system on the outer layer amba/axi.
简短的回答是，你需要更具体哪些武装你所谈论的核心，然后，一旦你知道，找到该核心TRM，这将包括回答你的问题。
The short answer is you need to be more specific about which arm core you are talking about, and then once you know that find the TRM for that core, and it will include the answer to your question.
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