问题描述
第 12 页的 Verilog 黄金参考指南警告不可合成的 always 块，并提供可遵循的模板以减少无意中创建不可合成的 always 块的机会.但是，该指南没有解释 always 块为什么以及在什么情况下是不可综合的.
The Verilog Golden Reference Guide on page 12 warns against unsynthesisable always blocks, and gives templates to be followed to reduce the chances of inadvertently creating unsynthesisable always blocks. However, the guide does not explain why, and in which situations, an always block is not synthesisable.
always 块不可综合的最常见原因是什么?
What are the most common reasons for an always block to not be synthesisable?
推荐答案
基本上每个always块都在描述一组触发器、一组锁存器或一组组合电路.
Basically every always block is describing a group of flip-flop, a group of latch, or a block of combinational circuit.
这三个编码格式不同，不能混用，否则可能无法合成.(有时锁存器和组合电路混用但应避免)
These three have different coding formats and should not be mixed, otherwise it may not be synthesizable. (sometime latch and combination circuit and be mixed but should be avoided)
任何不能映射到这三种类型电路的always块都是不可合成的.
Any always blocks that cannot be mapped to these three types of circuits are not synthesizable.
例如，信号和边沿的混合敏感列表是不可综合的，因为触发器不能同时进行边沿触发和电平触发.
For example, mixed sensitive list of signals and edges is not synthesizable, because a flip-flop cannot be edge-tiggered and level-triggered at the same time.
不能合成两个以上的时钟.
More than two clocks are not synthesizable.
嵌入的always块不可合成.
Embedded always blocks are not synthesizable.
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