如何将可合成延迟置于 FSM 状态

问题描述

涉及在移动到另一个状态之前要执行的特定延迟的 FSM 代码如下所示:

The code for the FSM which involves particular delay to be executed before moving to another state is as shown below:

module INIT_FSM(sys_DLY_100US,sys_CLK,sys_INIT_DONE,iState,sys_RESET);

input sys_DLY_100US;
input sys_CLK;
inout sys_INIT_DONE;
output [4:0] iState;
input sys_RESET;

wire sys_DLY_100US,sys_CLK;
reg [4:0] iState;
wire sys_INIT_DONE;
reg [4:0] NextState;

parameter i_NOP=5'b00000;
parameter i_PRE=5'b00001;
parameter i_tRP=5'b00010;
parameter i_AR1=5'b00011;
parameter i_tRFC1=5'b00100;
parameter i_AR2=5'b00101;
parameter i_tRFC2=5'b00110;
parameter i_MRS=5'b00111;
parameter i_tMRD=5'b01000;
parameter i_ready=5'b01001;


assign sys_INIT_DONE =(iState==5'b01001) ? 1'b1 : 1'bz;

always @(*)
begin
    NextState=iState;


    case (iState)

       5'b00000:
       begin
           if(sys_DLY_100US==1'b1)
           begin
               NextState=i_PRE;
           #10;
           end
       end

       5'b00001:
       begin
           NextState=i_AR1;
           #10;
       end

       5'b00011:
       begin
           NextState=i_AR2;
           #10;
       end

       5'b00101:
       begin
           NextState=i_MRS;
           #10;
       end

       5'b00111: NextState=i_ready;

       5'b01001:sys_INIT_DONE=1;
    endcase
end

always @(posedge sys_CLK or posedge sys_RESET)
    if(sys_RESET) iState <=i_NOP;
    else          iState <=NextState;
endmodule

这里不是代码中提到的每个状态的 #10，我如何通过另一种方法添加延迟以使其可合成?

Here instead of #10 in every state as mentioned in the code, how I could add delay by another method so that it is synthesizable?

推荐答案

# 延迟是不可合成的.

The # delays are not synthesizable.

如果你想在硬件中做一些时间相关的事情，你必须使用计数器来计算你的时钟周期.

If you want to do something time dependent in hardware you have to use a counter to count your clock cycles.

比较您状态中的计数值，并在达到延迟时更改状态并重置计数器.

Compare the count value in you states and change the state and reset the counter when your delay is reached.

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