ACTIV HDL - VHDL-“信号无法合成，同步描述错误"

问题描述

在 Xilinx 中合成此代码时出错.这个错误是:

I have a error while Synthesize this code in Xillinx. This error is:

信号Z_1无法合成，同步描述错误"

entity uk3 is
     port(
         rst : in BIT;
         C : in INTEGER;
         clk : in BIT;
         S : out INTEGER
         );
end uk3;

--}} End of automatically maintained section

architecture uk3 of uk3 is
begin
    process (C,clk,rst)
    variable Z_1 : integer:=0;
    begin
        if rst='1' then Z_1:=0;
        elsif rst='0'and clk'event and clk='1'and C=1
            then
            Z_1:=Z_1 + 1;
        elsif rst='0'and clk'event and clk='1'and C=2
            then
            Z_1:=Z_1 + 2;
        else
            Z_1:=Z_1;
        end if;
        S<=Z_1;
        end process;

     -- enter your statements here --

end uk3;

为什么?

推荐答案

您有一个 if 子句，其中包含对复位条件的检查，然后是两个单独的门控时钟条件，然后是一个 else 子句.我认为没有任何工具可以综合这些，因为您实际上不太可能想要您所描述的内容，而且无论如何都很难放入硬件.您需要阅读更多有关 HDL 和同步设计的基础知识.

You have an if clause that contains a check for reset condition, then two separate gated clock conditions and then an else clause. I don't think there's any tool that will synthesize this, because it's highly unlikely you actually want what you describe and it'd be reasonably hard to put in hardware anyway. You need to read more about the basics of HDL and synchronous design.

这样想:如果您像编译器一样从上到下逐行阅读您编写的代码，您实际上将如何构建能够执行您所描述的硬件?你如何构建一个硬件，在一个时钟上做一件事，在另一个时钟上做另一件事，而当根本不应用时钟时又做第三件事?您如何在 FPGA LUT 中实现这一点?

Think about it this way: If you read the code you wrote from top to bottom, line for line, as the compiler does, how would you actually go about building hardware that does what you described? How do you build a piece of hardware that does one thing on one clock, another thing on another clock and a third thing when no clock at all is applied? How do you implement this in your FPGAs LUTs?

简而言之，为了让你的代码工作，你需要去掉 else 子句，无论如何它什么都不做，合成器通常不喜欢 else 或elsif 子句与时钟条件(ifrising_egde(clk) 或 if clk'event and clk = '1')一起使用.C 的条件应在主时钟语句内的单独 if 子句中检查.另外，去掉 elsif 子句中对 rst = '0' 的检查.您已经在 if 语句中检查了 rst = '1' 并且 bit 信号只能是 '1' 或0".

In short, to get your code to work, you need to get rid of the else clause, it does nothing anyway and synthesizers generally don't like else or elsif-clauses alongside a clocking conditional(if rising_egde(clk) or if clk'event and clk = '1'). The condition of C should be checked in a separate if clause inside your main clocked statement. Also, get rid of the check for rst = '0' in the elsif clause. You already checked for rst = '1' in the if statement and a bit signal can only be '1' or '0'.

可合成的代码如下所示:

Synthesizable code would look like this:

process (clk, rst)
   if rst = '1' then
       -- your reset condition
   elsif clk'event and clk = '1' then -- if you use a bit type clk, otherwise use elsif rising_edge(clk) then
       if signal = condition then
          -- whatever you need doing
       else
          -- whatever you need doing
       end if;
   end if;
end process;

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