VHDL-“信号无法合成，同步描述不正确"

问题描述

在Xillinx中合成此代码时出现错误.该错误是:信号Z_1无法合成，同步描述不正确"

I have a error while Synthesize this code in Xillinx. This error is:"Signal Z_1 cannot be synthesized, bad synchronous description"

entity uk3 is
     port(
         rst : in BIT;
         C : in INTEGER;
         clk : in BIT;
         S : out INTEGER
         );
end uk3;

--}} End of automatically maintained section

architecture uk3 of uk3 is
begin
    process (C,clk,rst)
    variable Z_1 : integer:=0;
    begin
        if rst='1' then Z_1:=0;
        elsif rst='0'and clk'event and clk='1'and C=1
            then
            Z_1:=Z_1 + 1;
        elsif rst='0'and clk'event and clk='1'and C=2
            then
            Z_1:=Z_1 + 2;
        else
            Z_1:=Z_1;
        end if;
        S<=Z_1;
        end process;

     -- enter your statements here --

end uk3;

为什么?请

推荐答案

您可能应该正确地描述您的同步过程.这不是c/c ++，您应该为此使用适当的模板，否则它将无法合成.特别是，您应该只对时钟的边缘敏感.

You probably should properly describe your synchronous process. This is not c/c++, you should use proper template for that, or it will not synthesize. I particular, you should only have one statement sensitive for edge of the clock.

例如:

process (clk,rst)
variable Z_1 : integer:=0;
begin
    if rst='1' then
        Z_1:=0;
    elsif rising_edge(clk) then
        case C is
            when 1 =>
                Z_1:=Z_1 + 1;
            when 2 =>
                Z_1:=Z_1 + 2;
            when others =>
                null;
        end case;
        S<=Z_1;
    end if;

end process;

请注意，灵敏度列表中没有C，因为它不是必需的.如果没有上升沿，它将不会触发(与时钟的上升沿同步)

Note, that there is no C in sensitivity list, as it is not needed. If there is no rising edge, it will not fire anyway (it is synchronous to rising edge of the clock)

我没有测试过此代码，但它应该可以工作.

I havn't tested this code, but it should work.

实际上，为什么不发出Z_1信号，而不是发出可变信号?

And actually, why don't you make Z_1 signal, instead of variable?

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