问题描述
所以我开始争论多核 CPU 是否允许并行执行不同的进程.
据我所知，每个内核都允许执行不同的线程，但它们都必须属于一个进程.还是我错了?
我的理由是，虽然每个内核都有独立的一组寄存器和 L1/L2 缓存(取决于硬件)，但它们都必须共享其他东西，如 L3 缓存或 TLB(我对cpu 架构，所以请随时纠正我).
我试图寻找答案，但找不到任何结果(可能这个问题太愚蠢了哈哈).
非常感谢提前.
可以调度多个进程的多个线程在单个内核上运行.当然，在给定时间只有一个线程在核心上运行.要在核心上运行的进程队列由调度程序管理.一个好的调度器将为核心提供 CPU 密集型和 I/O 密集型进程的良好组合，以便机器中的所有组件都具有良好的负载平衡.
因此，多核 CPU 不仅允许进程并行执行，还允许进程并发执行.另一方面，单核 CPU 只能允许并行执行.单核机器没有并发.
一个核心的所有资源都分配给当前在其上运行的线程/进程(但不是在超线程中).如果我没记错的话，同时拥有多个进程的第一个资源是主内存或 RAM.所有进程都使用 RAM 的一部分，即使它们没有在核心上运行.为了将进程加载到内核，进程控制块 (PCB) 通过将寄存器、地址空间和堆栈设置为进程所处的相同状态，从 RAM 加载进程控制块 (PCB)，当它从内核卸载时，为另一个进程提供时间.
每个进程的时间量从
So I got into a debate whether multicore CPU allows parallel execution of separate processes.
As far as I understand, each core allows executing different threads but they all have to belong to one process. Or am I wrong?
My reasoning is that, while each core has separate set of registers and L1/L2 cache (depending on hardware), they all have to share other stuff like L3 cache or TLB (I don't have a lot of knowledge about cpu architecture, so feel free to correct me).
I tried searching for an answer, but couldn't find any results (maybe the question is too dumb lol).
Thanks a lot in adance.
Multiple threads of multiple processes can be scheduled to run on a single core. Of course, at a given time only one thread runs on the core. The queue of processes to run on the core is managed by the scheduler. A good scheduler will provide to the core a good mix of CPU-bound and I/O-bound processes so that all of the components in the machine have well-balanced load.
So a multi-core CPU allows not only parallel but also concurrent execution of processes. On the other hand, a single core CPU can allow only parallel execution. No concurrency is there in single core machines.
All the resources of a core are given to the thread/process currently running on it (not in Hyper Threading though). The first resource that is in possession of multiple processes at the same time, if I'm not wrong, is Main Memory or RAM. All processes use some part of the RAM even when they are not running on the core. To load the process to the core a Process Control Block (PCB) is loaded from RAM by setting the registers, address spaces and stack to the same state which the process was in, when it was unloaded from the core to give time to another process.
The time quantum for each process varies from a few ms to a few hundred ms. Compared to that a L1/L2 cache access is a few ns and a main memory access is a few hundred ns. The image below should be interesting:
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