本文介绍了我想要一个可合成的代码来将输出保存在 verilog,,,,in vertex 6 kit 中的文件中的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我的代码如下

reg [7:0] c[1:1000];
@(posedge clk)
begin
g=fopen(aa.txt,"w");
for(i=0;i<1000;i=i+1)
begin
$fdisplay(g,"%b",c[i]); end
$fclose(g);

但是这个代码是不可合成的.我需要一个可合成的代码.

but this code is not synthesizable.i neeed a synthesizable code.

我正在使用 vertex 6 套件

I am using a vertex 6 kit

推荐答案

要完成此任务(将 1000 字节数组的内容保存到某个存储介质中的文件中),您唯一的选择是实例化某种处理器(例如例如 MicroBlaze),并将其连接到您的 FPGA 板所具有的任何媒体(SD、Compact Flash、SATA、IDE 等)和您的 1000 字节阵列.然后,搜索一个 C 库来处理一些文件系统,如 FAT,并编写一个程序,遍历 1000 字节数组,读取它并使用 C 库创建一个文件,存储从数组中读取的字节,最后,关闭文件.

To accomplish this task (save the contents of a 1000 byte array to a file in some storage media) you only choice is to instantiate some kind of processor (like a MicroBlaze for example) in your design, and interface it to whatever media your FPGA board has (SD, Compact Flash, SATA, IDE, etc), and your 1000 byte array. Then, search for a C library to handle some filesystem like FAT, and write a program that iterates through the 1000 byte array, reading it and using the C library to create a file, store the bytes read from the array and finally, close the file.

这是可能的,但不仅仅是您发布的 Verilog 代码.您需要在 FPGA 中构建一个完整的 SoC 来处理它.

It's possible, but not just with the Verilog code you posted. You need to build an entire SoC in your FPGA to deal with it.

另一种资源需求更少的可能性是使用 FPGA 板上的内置设备通过串行端口或 USB 发送 1000 字节数组,在您的 PC 中接收它并从那里保存到磁盘.

Another possibility, much less resource demanding, is to use the built-in devices in your FPGA board to send the 1000 byte array through a serial port or USB, receive it in your PC and save to disk from there.

如果您的电路板中没有通信设备,您甚至可以构建一个 FSK 编码器,并将阵列内容作为一系列音调传输,就像旧调制解调器甚至旧 80 年代计算机所做的那样.使用声卡和一些软件来捕获 PC 中的数据以解码音频信号.为此,您唯一需要的资源是 FPGA 中配置为输出的引脚.

If you lack communication devices in your board, you can even build a FSK encoder, and transmit the array contents as series of tones, like old modems or even old 80's computers did. Capture the data in your PC using your sound card and some software to decode the audio signal. For this, the only resource you need is a pin configured as output, from your FPGA.

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08-22 18:50