问题描述
entity timer is
Port ( click : in STD_LOGIC;
clear : out STD_LOGIC;
t_unlock : out STD_LOGIC);
end timer;
architecture Behavioral of timer is
signal temp2 : integer range 0 to 20 := 0;
begin
process
begin
if rising_edge(click) then
temp2<=0;
clear<='0';
t_unlock<='0';
else
temp2<=temp2+1 after 15 ns;
end if;
if temp2=6 then
clear<='1';
elsif temp2=20 then
t_unlock<='1';
end if;
end process;
end Behavioral;
我写了这段代码.编译器说:
I have writted this code.And the complier say:
Signal temp2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
我在 stackoverflow 上搜索过.他们说 错误'bad synchronousdescription' 通常表示您描述了硬件中不存在的寄存器(时钟元素).但我不知道如何解决我的问题.
I have searched on stackoverflow.They say The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware.But I don't know how to solve my problem.
推荐答案
VHDL 必须遵循一些综合工具特定的编码指南,以便该工具能够将 VHDL 代码转换为 FPGA 实现.对于异步复位触发器的实现,样式可以是:
The VHDL has to follow some synthesis tool specific coding guidelines, for the tool to be able to translate the VHDL code into the FPGA implementation. For implementation to a flip-flop with asynchronous reset, the style can be:
process (clk, rst) is
begin
-- Clock
if rising_edge(clk) then
... -- Update at clock
end if;
-- Asynchronous reset
if rst = '1' then
... -- Update at reset
end if;
end process;
就您的代码而言,您似乎没有使用异步重置,因此模板可能会简化为:
In the case of your code it looks like you are not using the asynchronous reset, thus the template may be reduced to:
process (clk) is
begin
if rising_edge(clk) then
... -- Update at clock
end if;
end process;
现在的练习是让您将代码放入该模板中,不幸的是,很难根据提供的代码确定确切的意图.
The exercise is now for you to fit your code into that template, and unfortunately it is pretty hard to determine the exact intention based on the provided code.
这篇关于信号temp2无法合成,同步描述不好的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持!