I²C write access can be used to write a data byte in one sequence.
The sequence begins with start condition generated by the master, followed by 7 bits slave
address and a write bit (RW = 0). The slave sends an acknowledge bit (ACK = 0) and releases
the bus. Then the master sends the one byte register address. The slave again acknowledges
the transmission and waits for the 8 bits of data which shall be written to the specified register
address. After the slave acknowledges the data byte, the master generates a stop signal and
terminates the writing protocol.
Example of an I²C write access:
I²C写访问可用于在一个序列中写入数据字节。
序列从主设备生成的开始条件开始，然后是7位从设备
地址和写入位（RW＝0）。从设备发送一个确认位（ACK=0）并释放
公共汽车。然后主机发送一个字节的寄存器地址。奴隶再次承认
传输并等待将写入指定寄存器的8位数据
住址从设备确认数据字节后，主设备生成停止信号
终止写入协议。
I²C写访问示例：
I²C read access:
I²C read access also can be used to read one or multiple data bytes in one sequence.
A read sequence consists of a one-byte I²C write phase followed by the I²C read phase. The two
parts of the transmission must be separated by a repeated start condition (Sr). The I²C write
phase addresses the slave and sends the register address to be read. After slave acknowledges
the transmission, the master generates again a start condition and sends the slave address
together with a read bit (RW = 1). Then the master releases the bus and waits for the data bytes
to be read out from slave. After each data byte the master has to generate an acknowledge bit
(ACK = 0) to enable further data transfer. A NACKM (ACK = 1) from the master stops the data
being transferred from the slave. The slave releases the bus so that the master can generate a
STOP condition and terminate the transmission.
The register address is automatically incremented and, therefore, more than one byte can be
sequentially read out. Once a new data read transmission starts, the start address will be set to
the register address specified in the latest I²C write command. By default the start address is set
at 0x00. In this way repetitive multi-bytes reads from the same starting address are possible.
In order to prevent the I²C slave of the device to lock-up the I²C bus, a watchdog timer (WDT) is
implemented in the BMM150. The WDT observes internal I²C signals and resets the I²C interface
if the bus is locked-up. The activity and the timer period of the WDT is predefined with a default
time period of 50 ms by factory trimming.
I²C读取访问：
I²C读访问也可用于在一个序列中读取一个或多个数据字节。
读取序列由一个字节的I²C写入阶段和I²C读取阶段组成。两个
变速器的各部分必须由重复起动条件（Sr）分开。I²C写入
phase寻址从设备并发送要读取的寄存器地址。从机确认后
在传输过程中，主设备再次生成启动条件并发送从设备地址
以及读取位（RW＝1）。然后主机释放总线并等待数据字节
从奴隶身上读出。在每个数据字节之后，主机必须生成一个确认位
（ACK＝0）以使得能够进行进一步的数据传输。来自主机的NACKM（ACK=1）停止数据
从奴隶身上转移。从设备释放总线，以便主设备可以生成
STOP条件并终止变速器。
寄存器地址会自动递增，因此可以有多个字节
按顺序读出。一旦新的数据读取传输开始，起始地址将设置为
最新的I²C写入命令中指定的寄存器地址。默认情况下，已设置起始地址
在0x00。通过这种方式，从相同的起始地址重复读取多字节是可能的。
为了防止设备的I²C从设备锁定I²C总线，看门狗计时器（WDT）
在BMM150中实现。WDT观察内部I²C信号并重置I²C接口
如果公共汽车被锁住了。WDT的活动和定时器周期是用默认值预定义的
50毫秒的时间周期，通过工厂微调。
做过adxl345 人家是读写位分开 写两个地址，这个bmm150是写一个地址，如果没有mpu6050的示例，我根本不会研究出来，厂家真是应该多给点示例呀，这就跟上学是的，什么知识都会了，写不出代码来，做不出产品来，
现在讲讲，这些翻译写的是什么意思呢？ 就是代码应该是：
#define bmm150address 0X10
这是IIC代码，如果您有mpu6050的源码，对照改一下就行了，我只是借宝地记录一下
u8 bmm150_RD_Reg(u8 addr)
{
u8 temp=0;
IIC_Start();
IIC_Send_Byte( (bmm150address<<1)|0); //发送写器件指令
temp=IIC_Wait_Ack();
// printf("intaa:%d",temp); //pandaun
IIC_Send_Byte(addr); //发送寄存器地址
temp=IIC_Wait_Ack();
IIC_Start(); //重新启动
IIC_Send_Byte( (bmm150address<<1)|1); //发送读器件指令
temp=IIC_Wait_Ack();
temp=IIC_Read_Byte(0); //读取一个字节,不继续再读,发送NAK //读1个字节，ack=1时，发送ACK，ack=0，发送nACK
IIC_Stop(); //产生一个停止条件
return temp; //返回读到的值
}